1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display device, and more particularly, to a circuit for generating gate pulse modulation signal for a liquid crystal display device. Embodiments of the present invention are suitable for a wide scope of applications. In particular, embodiments of the present invention are suitable for reducing the appearance of flickers in a liquid crystal display device.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device includes a liquid crystal panel having gate lines and data lines and a gate driver for supplying gate signals to the gate lines. The gate driver is constructed such that a driver chip is mounted on a flexible printed circuit board at an edge portion of the liquid crystal panel. Recently, however, a GIP (gate in panel) technique has been employed to mount the gate driver on the liquid crystal panel.
A driving method of the gate driver can be classified into a non-overlapping driving method and an overlapping driving method. According to the non-overlapping driving method, the gate driver is operated in synchronization with a single clock signal (FLK) sequentially provided. According to the overlapping driving method, the gate driver is operated in synchronization with two non-overlapping clock signals (2-phase non-overlapping clocks).
FIG. 1 shows an example of a gate pulse modulation signal generated with a non-overlapping driving method according to the related art. Referring to FIG. 1(a), a single clock signal FLK is provided. A gate on voltage modulation signal VGHM is generated in synchronization with the single clock signal FLK, as shown in FIG. 1(b). The generated VGHM signal is level-shifted to generate a final gate output signal as shown in FIG. 1(c).
FIG. 2 shows an example of gate pulse modulation signals generated with the overlapping driving method according to the related art. Referring to FIG. 2, a clock signal FLK is provided as shown in FIG. 2(a). A gate ON voltage modulation signal VGHM is generated in synchronization with the clock signal FLK as shown in FIG. 2(b). As shown in FIGS. 2(c) to 2(e), the gate driver of the liquid crystal panel generates gate output signals, each having a period of 2 H and two modulation intervals using a gate high voltage VGH and a gate low voltage VGL. The gate output signals shown in FIGS. 2(c) to 2(e) have a dipping point at a middle portion thereof, making charging unstable and causing defects on the display panel, such as a vertical line.
FIG. 3 shows other examples of gate pulse modulation signals generated with the overlapping driving method according to the related art. Referring to FIG. 3, gate pulse modulation signals are generated using clock signals that can cover the period 2 H. Specifically, as shown in FIG. 3(a), a clock signal FLK is provided that can cover a period 2 H. A gate ON voltage modulation signal VGHM is generated in synchronization with the clock signal FLK as shown in FIG. 3(b). The VGHM signal is level-shifted to generate final gate output signals as shown in FIGS. 3(c) to 3(e). In this case, however, because gate modulation is made only at the middle portion of the gate output signal as shown in FIG. 3D, a desired output waveform cannot be obtained.
In accordance with the related art using a single clock signal FLK, when the overlapping driving method is applied to the gate lines in a GIP circuit to improve charging characteristics of the signals, because the period of the gate output is 2 H, it is not possible to output a signal for simultaneously modulating outputs of the odd-numbered gate lines and the even-numbered gate lines.